FEX-2605
May 9, 2026 ยท View on GitHub
FEXCore
See FEXCore/Readme.md for more details
Glossary
- Splatter: a code generator backend that concatenates configurable macros instead of doing isel
- IR: Intermediate Representation, our high-level opcode representation, loosely modeling arm64
- SSA: Single Static Assignment, a form of representing IR in memory
- Basic Block: A block of instructions with no control flow, terminated by control flow
- Fragment: A Collection of basic blocks, possibly an entire guest function or a subset of it
backend
IR to host code generation
arm64
- ALUOps.cpp
- Arm64Relocations.cpp: relocation logic of the arm64 splatter backend
- AtomicOps.cpp
- BranchOps.cpp
- ConversionOps.cpp
- EncryptionOps.cpp
- JIT.cpp: Main glue logic of the arm64 splatter backend
- JITClass.h
- MemoryOps.cpp
- MiscOps.cpp
- MoveOps.cpp
- VectorOps.cpp
shared
frontend
x86-meta-blocks
- Frontend.cpp: Extracts instruction & block meta info, frontend multiblock logic
x86-tables
- BaseTables.cpp
- DDDTables.cpp
- H0F38Tables.cpp
- H0F3ATables.cpp
- PrimaryGroupTables.cpp
- SecondaryGroupTables.cpp
- SecondaryModRMTables.cpp
- SecondaryTables.cpp
- VEXTables.cpp
- X86Tables.h
- X87Tables.cpp
x86-to-ir
- AVX_128.cpp: Handles x86/64 AVX instructions to 128-bit IR
- Crypto.cpp: Handles x86/64 Crypto instructions to IR
- Flags.cpp: Handles x86/64 flag generation
- Vector.cpp: Handles x86/64 Vector instructions to IR
- X87.cpp: Handles x86/64 x87 to IR
- X87F64.cpp: Handles x86/64 x87 to IR
- OpcodeDispatcher.cpp: Handles x86/64 ops to IR, no-pf opt, local-flags opt
glue
Logic that binds various parts together
block-database
- LookupCache.cpp: Stores information about blocks, and provides C++ implementations to lookup the blocks
driver
Emulation mainloop related glue logic
- Core.cpp: Glues Frontend, OpDispatcher and IR Opts & Compilation, LookupCache, Dispatcher and provides the Execution loop entrypoint
log-manager
thunks
ir
debug
- IRDumperPass.cpp: Prints IR
dumper
IR -> Text
emitter
C++ Functions to generate IR. See IR.json for spec.
opts
IR to IR Optimization
- PassManager.cpp: Defines which passes are run, and runs them
- PassManager.h
- IRValidation.cpp: Sanity checking pass
- RedundantFlagCalculationElimination.cpp
- RegisterAllocationPass.cpp
- RegisterAllocationPass.h
opcodes
cpuid
- CPUID.cpp: Handles presented capability bits for guest cpu
dispatcher-implementations
- AVX_128.cpp: Handles x86/64 AVX instructions to 128-bit IR
- Crypto.cpp: Handles x86/64 Crypto instructions to IR
- Flags.cpp: Handles x86/64 flag generation
- Vector.cpp: Handles x86/64 Vector instructions to IR
- X87.cpp: Handles x86/64 x87 to IR
- X87F64.cpp: Handles x86/64 x87 to IR
- OpcodeDispatcher.cpp: Handles x86/64 ops to IR, no-pf opt, local-flags opt
ThunkLibs
See ThunkLibs/README.md for more details
thunklibs
These are generated + glue logic 1:1 thunks unless noted otherwise
EGL
- libEGL_Guest.cpp: Depends on glXGetProcAddress thunk
- libEGL_Host.cpp
GL
- libGL_Guest.cpp: Handles glXGetProcAddress
- libGL_Host.cpp: Uses glXGetProcAddress instead of dlsym
SDL2
- libSDL2_Guest.cpp: Handles sdlglproc, dload, stubs a few log fns
- libSDL2_Host.cpp
VDSO
- libVDSO_Guest.cpp: Linux VDSO thunking
Vulkan
asound
drm
fex_malloc
- Guest.cpp: Handles allocations between guest and host thunks
- Host.cpp: Handles allocations between guest and host thunks
fex_malloc_loader
- Guest.cpp: Delays malloc symbol replacement until it is safe to run constructors
fex_malloc_symbols
- Host.cpp: Allows FEX to export allocation symbols
fex_thunk_test
wayland-client
xshmfence
Source/Tests
unittests
See unittests/Readme.md for more details