defs.md

July 26, 2026 · View on GitHub

Public entry point to all supported Verilog rules and APIs

verilog_dv_library

verilog_dv_library(name, deps, dpi, in_flist, incdir, makelib, srcs)

A DV Library.

Creates a generated flist file from a list of source files.

Generated paths use Bazel short_path form so the flist is rooted at the
runfiles tree (for example `hw/...` and `external/...`). Hand-authored nested
filelists should prefer the same style and avoid `../` upward traversals.

Recommended DPI usage is to keep SystemVerilog files in `srcs`/`in_flist` and
provide shared libraries through the `dpi` attribute, for example:

cc_binary(
    name = "dpi",
    srcs = glob(["*.c"]),
    linkshared = True,
)

verilog_dv_library(
    name = "pkg",
    srcs = glob(["*.sv"]),
    dpi = [":dpi"],
)

ATTRIBUTES

Name	Description	Type	Mandatory	Default
name	A unique name for this target.	Name	required
deps	verilog_dv_library targets that this target is dependent on.	List of labels	optional	[]
dpi	Shared libraries to load through the DPI. Build source-based DPI libraries with `cc_binary(linkshared = True)` and pass that target here. Currently, cc_import is not supported for precompiled shared libraries. Prefer placing shared libraries here rather than globbing `.so` files into `srcs`. Example: `cc_binary(name = "dpi", srcs = glob([".c"]), linkshared = True)` then `verilog_dv_library(name = "pkg", srcs = glob([".sv"]), dpi = [":dpi"])`.	List of labels	optional	[]
in_flist	Files to be placed directly in the generated flist. Best practice recommends 'pkg' and 'interface' files be declared here. If this attribute is empty (default), all srcs will put into the flist instead.	List of labels	optional	[]
incdir	Generate a +incdir in generated flist for every file's directory declared in 'srcs' attribute.	Boolean	optional	True
makelib	Compile this target into the named Xcelium library through `-makelib`/`-endlib`. VCS receives the same ordered sources through a separate `-file` boundary; VCS recompilation isolation is provided by `-Mupdate` and Partition Compile rather than Xcelium library syntax.	String	optional	`""`
srcs	Systemverilog source files. Files are assumed to be <code>included inside another file (e.g. the package file) and will not be placed on directly in the flist unless declared in the 'in_flist' attribute.	List of labels	required

verilog_dv_tb

verilog_dv_tb(name, ccf, defines, deps, dut_instance, dut_top, extra_compile_args, extra_runfiles,
              extra_runtime_args, msie_incremental_deps, msie_incremental_extra_compile_args, msie_incremental_extra_runfiles, msie_primary_deps, msie_primary_extra_compile_args, msie_primary_extra_runfiles, run_fail_patterns, run_pass_patterns, shells, simulator, vcs_cm_hier, vcs_elab_args, vcs_three_step, vcs_vlogan_args, vcs_vlogan_precompile_deps, verilog_config, warning_waivers, xcelium_covfile)

A DV Testbench.

rules_verilog uses two separate rules to strongly differentiate between
compilation and simulation. verilog_dv_tb is used for compilation and    
verilog_dv_test_cfg is used for simulation.

A verilog_dv_tb describes how to compile a testbench. It is not a
standalone executable bazel rule. It is intended to provide simmer (a
higher level simulation spawning tool) hooks to execute the compile and
subsequent simulations.

The compile and runtime filelists are generated according to the selected
simulator. The generated file names are `<name>_compile_args.f` and
`<name>_runtime_args.f`.

ATTRIBUTES

Name	Description	Type	Mandatory	Default
name	A unique name for this target.	Name	required
ccf	Xcelium coverage configuration file. At most one file is accepted; VCS coverage uses `-cm` options instead.	List of labels	optional	[]
defines	Additional preprocessor defines to throw for this testbench compile. Key, value pairs are joined without additional characters. If it is a unary flag, set the value portion to be the empty string. For binary flags, add an '=' as a suffix to the key.	Dictionary: String -> String	optional	{}
deps	A list of verilog_dv_library or verilog_rtl_library labels that the testbench is dependent on. Dependency ordering within this label list is not necessary if dependencies are consistently declared in all other rules.	List of labels	required
dut_instance	DUT instance hierarchy used by coverage reports.	String	optional	`"hdl_top.dut"`
dut_top	DUT module name used to scope code coverage.	String	optional	`"dut"`
extra_compile_args	Additional flags to pass to the selected simulator compile/elaboration step. VCS three-step targets must instead split these options between `vcs_vlogan_args` and `vcs_elab_args`.	List of strings	optional	[]
extra_runfiles	Additional files that need to be passed as runfiles to bazel. Most commonly used for files referred to by extra_compile_args or extra_runtime_args.	List of labels	optional	[]
extra_runtime_args	Additional flags passed only to simulator runs. Runtime path arguments should use absolute paths or `bazel_runfiles_main/...` paths.	List of strings	optional	[]
msie_incremental_deps	Xcelium MSIE dependencies for the changing testbench/test partition. Configure together with msie_primary_deps.	List of labels	optional	[]
msie_incremental_extra_compile_args	Xcelium compile/elaboration flags used only while building the MSIE incremental snapshot.	List of strings	optional	[]
msie_incremental_extra_runfiles	Files referenced only by msie_incremental_extra_compile_args.	List of labels	optional	[]
msie_primary_deps	Xcelium MSIE dependencies for the stable primary DUT/netlist partition. Configure together with msie_incremental_deps.	List of labels	optional	[]
msie_primary_extra_compile_args	Xcelium compile/elaboration flags used only while building the MSIE primary snapshot.	List of strings	optional	[]
msie_primary_extra_runfiles	Files referenced only by msie_primary_extra_compile_args, such as primary SDF command files.	List of labels	optional	[]
run_fail_patterns	Additional regular expressions that identify a failed simulation.	List of strings	optional	[]
run_pass_patterns	Regular expressions that identify a successful simulation. When set, at least one must match.	List of strings	optional	[]
shells	List of shells to use. Each label must be a verilog_rtl_shell instance. Each shell thrown will create two defines: <code>define gumi_{module} {module}shell </code>define gumi_use{module}shell The shell module declaration must be guarded by the gumi_use{module}shell define: <code>ifdef gumi_use{module}_shell module {module}_shell(/AUTOARGS/); ... endmodule </code>endif	List of labels	optional	[]
simulator	Simulator to use for this DV testbench. Supported values are XRUN and VCS. The selected simulator determines which compile/runtime filelists are generated.	String	optional	`"XRUN"`
vcs_cm_hier	VCS `-cm_hier` coverage configuration file.	Label	optional	None
vcs_elab_args	Additional VCS elaboration options used only by `vcs` in `vcs_three_step` mode. Put `-top`, `+optconfigfile`, and other elaboration-only options here. Files referenced with `$(location)` must also be listed in `extra_runfiles`.	List of strings	optional	[]
vcs_three_step	Use VCS three-step analysis/elaboration. Dependencies selected by `vcs_vlogan_precompile_deps` form one frozen `vlogan -incr_vlogan` group, and remaining filelists form one project group. When enabled, `extra_compile_args` must be empty; put analysis options in `vcs_vlogan_args` and elaboration options in `vcs_elab_args`.	Boolean	optional	`False`
vcs_vlogan_args	Additional VCS analysis options used only by `vlogan` in `vcs_three_step` mode. Put preprocessor defines and other source-analysis options here, with one command-line argument per list item. Files referenced with `$(location)` must also be listed in `extra_runfiles`.	List of strings	optional	[]
vcs_vlogan_precompile_deps	Dependencies whose transitive VCS filelists form one frozen `vlogan -incr_vlogan` analysis group. Each selected dependency must already be reachable through `deps` or `shells`. The remaining filelists form one project analysis group. Top-level `.vh` and `.svh` entries from frozen filelists are replayed before the project group. Other preprocessor macros do not cross analysis groups, so the boundary must be self-contained and downstream sources must import compiled packages instead of depending on nested macro or include-guard side effects from the frozen group.	List of labels	optional	[]
verilog_config	Key/value pairs where each key is a Verilog configuration name and each value is the relative path to its configuration `.v` file.	Dictionary: String -> String	optional	{}
warning_waivers	Waive warnings in the compile. By default, simmer promotes all compile warnings to errors. This list is converted to python regular expressions which are imported by simmer to waive warning. Xcelium waivers commonly match '*W,<ID>'; VCS waivers commonly match 'Warning-[<ID>]'.	List of strings	optional	[]
xcelium_covfile	Xcelium coverage configuration file. Replaces the legacy `ccf` attribute.	Label	optional	None

verilog_dv_test_cfg

verilog_dv_test_cfg(name, tags, abstract, inherits, uvm_testname, tb, simulator, sim_opts, no_run, sockets, pre_run, timeout, description, gls_tb, pre_opts, post_opts, gatesim_modes)

A DV test configuration.

This is not a executable target. It generates multiple files which may then
be used by simmer (the wrapping tool to invoke the simulator).

ATTRIBUTES

Name	Description	Type	Mandatory	Default
name	A unique name for this target.	Name	required
tags	Bazel tags for the base configuration. Including `gatesim` also generates one configuration per `gatesim_modes` entry. Scheduling tags remain on the base configuration.	List of strings	optional	None
abstract	When True, this configuration is an inheritance-only base and may omit `tb`. Concrete configurations must resolve a testbench directly or through `inherits`.	Boolean	optional	False
inherits	Inherit configurations from other verilog_dv_test_cfg targets. Entries later in the list will override arguments set by previous inherits entries. Only attributes noted as inheritable in documentation may be inherited. Any field explicitly set in this rule will override values set via inheritance.	List of labels	optional	[]
uvm_testname	UVM testname eventually passed to simulator via plusarg +UVM_TESTNAME. This attribute is inheritable. See 'inherits' attribute.	String	optional	""
tb	The testbench to run this test on. This label must be a `verilog_dv_tb` target. It is inheritable and required after inheritance for every concrete configuration.	Label	optional	None
simulator	Simulator to use for this test configuration. Supported values are XRUN and VCS. This attribute is inheritable. Concrete configurations default to the associated testbench's simulator, then XRUN, and must match the testbench. An abstract configuration without a testbench may leave it unresolved.	String	optional	`""`
sim_opts	Additional runtime simulation options. The key/value pairs are concatenated; use an empty value for unary options and include `=` at the end of keys that take a value. Inherited dictionaries are merged in order and this configuration overrides matching keys.	Dictionary: String -> String	optional	{}
no_run	Set to True to skip running this test. This flag is not used by bazel but is used as a query filter by simmer.TODO: Deprecate this flag in favor of using built-in tags.	Boolean	optional	False
sockets	Dictionary mapping of socket_name to socket_command. Simmer has the ability to spawn parallel processes to the primary simulation that are connected via sockets. For each entry in the dictionary, simmer will create a separate process and pass a unique temporary file path to both the simulator and the socket_command. The socket name must match [A-Za-z_][A-Za-z0-9_]* and is passed as "+SOCKET__<socket_name>=<socket_file>" to the simulator. The socket_file is a short, unique path under /tmp created by simmer to stay within Unix-domain socket path limits. The socket_command is a bash command that must contain the literal placeholder "{socket_file}"; other shell braces are preserved. The socket_command will be run from the root of the project tree.	Dictionary: String -> String	optional	{}
pre_run	Bazel target to run immediately before simulation. This attribute is inheritable.	String	optional	None
timeout	Main simulation timeout in minutes, excluding socket and pre-run setup. This option is inheritable. Use -1 to inherit, 0 to disable, or a positive value to set a timeout.	Integer	optional	-1
description	The test simulation scenarios. (e.g. description = """ This is the test description """, )	String	optional	None
gls_tb	Base gate-level testbench label. When `gatesim` is tagged, each generated corner appends its mode to this label. If omitted, `tb` is used as the base.	Label	optional	None
pre_opts	Runtime option overrides merged into `sim_opts` for the base, pre-layout configuration.	Dictionary: String -> String	optional	None
post_opts	Runtime option overrides merged into `sim_opts` for generated gate-simulation corner configurations.	Dictionary: String -> String	optional	None
gatesim_modes	Suffixes used to generate gate-simulation configurations when `tags` includes `gatesim`.	List of strings	optional	`["nl", "sdf_wc", "sdf_lt", "tt_min", "tt_max"]`

verilog_dv_unit_test

verilog_dv_unit_test(name, compile_args, default_sim_opts, deps, run_args, sim_args, simulator, ut_sim_template)

Compiles and runs a small unit test for DV.

This is typically a unit test for a single verilog_dv_library and its dependencies.
Additional sim options may be passed after '--' in the bazel command.
Interactive example:
  bazel run //hw/dv/interfaces/apb_pkg:test -- -gui
For ci testing purposes:
  bazel test //hw/dv/interfaces/apb_pkg:test

ATTRIBUTES

Name	Description	Type	Mandatory	Default
name	A unique name for this target.	Name	required
compile_args	Additional arguments passed to compilation/elaboration. With VCS, legacy `-define NAME` entries become `+define+NAME`; Xcelium-only debug and wave flags are omitted.	List of strings	optional	[]
default_sim_opts	Default simulator options to pass to the simulator.	Label	optional	@rules_verilog//vendors/cadence:verilog_dv_unit_test_opts.f
deps	verilog_dv_library or verilog_rtl_library labels that the testbench is dependent on. Dependency ordering within this label list is not necessary if dependencies are consistently declared in all other rules.	List of labels	required
run_args	Additional arguments passed only to simulation runtime.	List of strings	optional	[]
sim_args	Deprecated compile arguments. Use `compile_args` and `run_args` instead. With VCS, legacy `-define NAME` entries become `+define+NAME`; Xcelium-only debug and wave flags are omitted.	List of strings	optional	[]
simulator	Simulator to use for this one-step unit test. When omitted, `verilog_unit_test_simulator` selects XRUN or VCS.	String	optional	`""`
ut_sim_template	The template to generate the bash script to run the simulation. Custom templates selected with VCS must implement the VCS compile-then-`simv` flow. Existing placeholders including `FLISTS`, `SIM_ARGS`, `COMPILE_ARGS`, and `RUN_ARGS` are available for both simulators.	Label	optional	@rules_verilog//vendors/cadence:verilog_dv_unit_test.sh.template

verilog_rtl_cdc_test

verilog_rtl_cdc_test(name, bash_template, bbox_array_size, bbox_modules, cmd_files, defines, deps,
                     epilogue_template, preamble_template, shells, top)

Run Jaspergold CDC on a verilog_rtl_library.

ATTRIBUTES

Name	Description	Type	Mandatory	Default
name	A unique name for this target.	Name	required
bash_template	The template for the generated bash script which will run the case.	Label	optional	//vendors/cadence:verilog_rtl_cdc_test.sh.template
bbox_array_size	Black box any RTL array greater than the specified size. If the value of this attribute is 0, the CDC tool will use the default size	Integer	optional	0
bbox_modules	List of modules to black box	List of strings	optional	[]
cmd_files	A list of tcl files containing commands to run. Multiple files are allowed to facilitate separating common project commands and block-specific commands.	List of labels	required
defines	List of additional <code>defines for this cdc run. LINT and CDC are always defined If a define is only for control and has no value, e.g. </code>define USE_AXI, the dictionary entry key should be "USE_AXI" and the value should be the empty string. If a define needs a value, e.g. <code>define WIDTH 8, the dictionary value must start with '=', e.g. '=8'	Dictionary: String -> String	optional	{}
deps	Other verilog libraries this target is dependent upon. All Labels specified here must provide a VerilogInfo provider.	List of labels	required
epilogue_template	The template to generate the final reporting commands for this cdc test.	Label	optional	@rules_verilog//vendors/cadence:verilog_rtl_cdc_epilogue_cmds.tcl.template
preamble_template	The template to generate the initial commands (the preamble) for this cdc test.	Label	optional	@rules_verilog//vendors/cadence:verilog_rtl_cdc_preamble_cmds.tcl.template
shells	List of verilog_rtl_shell Labels. For each Label, a gumi define will be placed on the command line to use this shell instead of the original module. This requires that the original module was instantiated using <code>gumi_<module_name> instead of just <module_name>.	List of labels	optional	[]
top	The name of the top-level module for this cdc run	String	required

verilog_rtl_library

verilog_rtl_library(name, deps, direct, enable_gumi, gumi_file_override, gumi_override, headers,
                    is_pkg, is_shell_of, lib_files, makelib, modules, no_synth)

A collection of RTL design files. Creates a generated flist file to be included later in a compile.

ATTRIBUTES

Name	Description	Type	Mandatory	Default
name	A unique name for this target.	Name	required
deps	Other verilog libraries this target is dependent upon. All Labels specified here must provide a VerilogInfo provider.	List of labels	optional	[]
direct	Verilog files that must be put directly onto the command line. 'modules' should be used instead of 'direct' wherever possible	List of labels	optional	[]
enable_gumi	When set and `gumi_file_override` is absent, create an additional file containing default preprocessor values for the gumi system.	Boolean	optional	True
gumi_file_override	Use the supplied Label or file as the GUMI definitions file instead of generating one. The override remains part of the library's transitive sources and runfiles.	Label	optional	None
gumi_override	A list of strings of module names to create gumi defines. If empty (default), the modules variable is used instead. Useful when using 'direct' or 'lib_files' or to limit the defines created when using a glob in 'modules'	List of strings	optional	[]
headers	Files that will be included into other files. A '+incdir' flag will be added for each source file's directory.	List of labels	optional	[]
is_pkg	INTERNAL: Do not set in verilog_rtl_library instances. Used for internal bookkeeping for macros derived from verilog_rtl_library. Used to enforce naming conventions related to packages to encourage simple dependency graphs	Boolean	optional	False
is_shell_of	INTERNAL: Do not set in verilog_rtl_library instances. Used for internal bookkeeping for macros derived from verilog_rtl_library. If set, this library is represents a 'shell' of another module. Allows downstream test rules to specify this Label as a 'shell' to override another instance via the gumi system.	String	optional	""
lib_files	Verilog library files containing multiple modules. A '-v' flag will be added for each file in this attribute. It is preferable to used the 'modules' attribute when possible because library files require parsing entire files to discover all modules.	List of labels	optional	[]
makelib	Compile this target into the named Xcelium library through `-makelib`/`-endlib`. VCS receives the same ordered sources through a separate `-file` boundary; VCS recompilation isolation is provided by `-Mupdate` and Partition Compile rather than Xcelium library syntax.	String	optional	`""`
modules	Verilog files containing a single module where the module name matches the file name. A '-y' flag will be added for each source file's directory. This is the preferred mechanism for specifying RTL modules.	List of labels	optional	[]
no_synth	Compatibility marker for downstream synthesis aspects or consumers. Simulation targets continue to include this library.	Boolean	optional	False

verilog_rtl_lint_test

verilog_rtl_lint_test(name, command_template, defines, deps, design_info, lint_parser, rulefile, rulefile_vcs,
                      run_template, shells, simulator, top, waiver_direct)

Compile and run lint on target

This rule was originally written for Cadence HAL to be run under xcelium. As such, it
is not entirely generic. It also uses a log post-processor
(passed in by the lint_parser attribute) to allow for easier waiving of warnings.

When `simulator = "VCS"`, the rule automatically switches to built-in
Synopsys defaults for the launcher, lint command file, parser, and default
rulefile. Projects may still override these assets if they need a more
opinionated local policy.

The DUT must have no unwaived warning/errors in order for this rule to
pass. The intended philosophy is for blocks to maintain a clean lint status
throughout the lifecycle of the project, not to run lint as a checklist
item towards the end of the project.

There are several attributes in this rule that must be kept in sync.
run_template, rulefile, lint_parser, and command_template must use the associated
files for each vendor. The default values auto-select between the built-in
Cadence and Synopsys sets based on the simulator attribute. If an instance
overrides any of these vendor-specific values, it should override the full set.

ATTRIBUTES

Name	Description	Type	Mandatory	Default
name	A unique name for this target.	Name	required
command_template	The template to generate the command script for this lint test. The command templates are located at @rules_verilog//vendors/<vendor name>/verilog_rtl_lint_cmds.tcl.template	Label	optional	@rules_verilog//vendors/cadence:verilog_rtl_lint_cmds.tcl.template
defines	List of additional <code>defines for this lint run. LINT is always defined by default If a define is only for control and has no value, e.g. </code>define USE_AXI, the dictionary entry key should be "USE_AXI" and the value should be the empty string. If a define needs a value, e.g. <code>define WIDTH 8, the dictionary value must start with '=', e.g. '=8'	Dictionary: String -> String	optional	{}
deps	Other verilog libraries this target is dependent upon. All Labels specified here must provide a VerilogInfo provider.	List of labels	required
design_info	A Cadence design_info file to add additional lint rule/waivers	List of labels	optional	[]
lint_parser	Post processor for lint logs allowing for easier waiving of warnings. Parsers for HAL, Ascent, and VCS are included in rules_verilog release at `@rules_verilog//bin:lint_parser_(hal	ascent	vcs)`. When left at the default HAL label and` simulator = "VCS"`, the rule automatically switches to the built-in VCS parser.	Label
rulefile	The rules configuration file for this lint run. Each project may write its own tool-specific rulefile. When omitted and `simulator = "VCS"`, rules_verilog uses a built-in Synopsys default lint opts file. When `simulator = "XRUN"`, a project-specific Cadence/HAL rulefile is still required. Example HAL rulefile: https://github.com/freecores/t6507lp/blob/ca7d7ea779082900699310db459a544133fe258a/lint/run/hal.def	Label	optional
rulefile_vcs	Optional VCS-specific lint options file. When simulator selection comes from the global VCS config, `rulefile` remains reserved for Cadence/HAL and this attribute overrides the built-in Synopsys defaults. Explicit `simulator = "VCS"` targets may continue using `rulefile` for backward compatibility.	Label	optional
run_template	The template to generate the script to run the lint test. The command templates are located at @rules_verilog//vendors/<vendor name>/verilog_rtl_lint_test.tcl.template	Label	optional	@rules_verilog//vendors/cadence:verilog_rtl_lint_test.sh.template
shells	List of verilog_rtl_shell Labels. For each Label, a gumi define will be placed on the command line to use this shell instead of the original module. This requires that the original module was instantiated using <code>gumi_<module_name> instead of just <module_name>.	List of labels	optional	[]
simulator	Simulator launcher to use for this lint test. When omitted, `verilog_unit_test_simulator` selects XRUN or VCS. XRUN uses the built-in Cadence defaults. VCS automatically switches to the built-in Synopsys launcher, lint command file, parser, and default rulefile.	String	optional	`""`
top	The name of the top-level module for this lint run	String	required
waiver_direct	Lint waiver python regex to apply directly to a lint message. This is sometimes needed to work around cases when HAL has formatting errors in xrun.log.xml that cause problems for the lint parser	String	optional	""

verilog_rtl_unit_test

verilog_rtl_unit_test(name, command_override, data, deps, post_flist_args, pre_flist_args, run_args, shells,
                      simulator, ut_sim_template, ut_sim_waves_template, wave_viewer_command)

Compile and simulate a verilog_rtl_library.

Allows a designer to write small unit/directed tests which can be included in regression.

This rule is capable of running SVUnit regressions as well. See ut_sim_template attribute.

This unit test can either immediately launch a waveform viewer, or it can render a waveform database which can be loaded separately.
To launch the waveform viewer after the test completes, run the following: 'bazel run <target> -- --launch &'.
To render a database without launching a viewer, run the following: 'bazel run <target> -- --waves'.
Any other unknown options will be passed directly to the simulator, for example: 'bazel run <target> -- --waves +my_arg=4'.

Typically, an additional verilog_rtl_library containing 'unit_test_top.sv'
is created. This unit_test_top will be dependent on the DUT top, and will
be the only entry in the `deps` attribute list provided to verilog_rtl_unit_test.

ATTRIBUTES

Name	Description	Type	Mandatory	Default
name	A unique name for this target.	Name	required
command_override	Allows custom override of simulator command in the event of wrapping via modulefiles. Example override in project's .bazelrc: build --@rules_verilog//:verilog_rtl_unit_test_command="runmod -t xrun --"	Label	optional	@rules_verilog//:verilog_rtl_unit_test_command
data	Non-verilog dependencies. Useful when reading in data files as stimulus/prediction.	List of labels	optional	[]
deps	Other verilog libraries this target is dependent upon. All Labels specified here must provide a VerilogInfo provider.	List of labels	required
post_flist_args	Additional command line arguments to be placed after the flist arguments. See ut_sim_template attribute for exact layout. With VCS, legacy `-define NAME` entries become `+define+NAME`; Xcelium-only debug and wave flags are omitted, and non-compiler plusargs are passed to `simv`.	List of strings	optional	[]
pre_flist_args	Additional command line arguments to be placed after the simulator binary but before the flist arguments. See ut_sim_template attribute for exact layout. For defines to have effect, they must be declared in pre_flist_args, not post_flist_args. With VCS, legacy `-define NAME` entries become `+define+NAME`; Xcelium-only debug and wave flags are omitted, and non-compiler plusargs are passed to `simv`.	List of strings	optional	[]
run_args	Additional arguments passed only to simulation runtime. With VCS, legacy runtime plusargs in `pre_flist_args` or `post_flist_args` are also passed to `simv`, or through `runSVUnit -r` for the bundled SVUnit template.	List of strings	optional	[]
shells	List of verilog_rtl_shell Labels. For each Label, a gumi define will be placed on the command line to use this shell instead of the original module. This requires that the original module was instantiated using <code>gumi_<module_name> instead of just <module_name>.	List of labels	optional	[]
simulator	Simulator to use for this one-step RTL unit test. When omitted, `verilog_unit_test_simulator` selects XRUN or VCS. VCS one-step wave dumping is currently disabled.	String	optional	`""`
ut_sim_template	The template to generate the script to run the test. The bundled SVUnit template @rules_verilog//vendors/cadence:verilog_rtl_unit_test_svunit.sh.template follows the configured simulator and maps to the Synopsys template under VCS. Custom templates remain simulator-specific. If using the SVUnit template, you may also want to throw: `post_flist_args = [ "--directory <path_to_test_directory_from_workspace>", ],`	Label	optional	@rules_verilog//vendors/cadence:verilog_rtl_unit_test.sh.template
ut_sim_waves_template	The template to generate the waves command script to run in the test. When using the bundled SVUnit template, use @rules_verilog//vendors/cadence:verilog_rtl_unit_test_svunit_waves.tcl.template. It maps to a disabled Synopsys placeholder under VCS because VCS one-step wave dumping is currently disabled. Custom SVUnit invocations must provide their own simulator-specific waves template.	Label	optional	@rules_verilog//vendors/cadence:verilog_rtl_unit_test_waves.tcl.template
wave_viewer_command	Allows custom override of waveform viewer command in the event of wrapping via modulefiles. Example override in project's .bazelrc: build --@rules_verilog//:verilog_rtl_wave_viewer_command="runmod xrun --"	Label	optional	@rules_verilog//:verilog_rtl_wave_viewer_command

verilog_test

verilog_test(name, data, deps, post_flist_args, pre_flist_args, shells, tool)

Provides a way to run a test against a set of libs.

ATTRIBUTES

Name	Description	Type	Mandatory	Default
name	A unique name for this target.	Name	required
data	Non-verilog dependencies	List of labels	optional	[]
deps	Other verilog libraries this target is dependent upon. All Labels specified here must provide a VerilogInfo provider.	List of labels	required
post_flist_args	Commands and arguments after flist arguments	List of strings	optional	[]
pre_flist_args	Commands and arguments before flist arguments	List of strings	optional	[]
shells	List of verilog_rtl_shell Labels. For each Label, a gumi define will be placed on the command line to use this shell instead of the original module. This requires that the original module was instantiated using <code>gumi_<module_name> instead of just <module_name>.	List of labels	optional	[]
tool	Label to a single executable tool to run. The executable and its default runfiles are available to the generated runner. Inserted before pre_flist_args if set. Do not duplicate in pre_flist_args.	Label	optional	None

verilog_tool_encapsulation

verilog_tool_encapsulation(name, build_setting_default)

ATTRIBUTES

Name	Description	Type	Mandatory	Default
name	A unique name for this target.	Name	required
build_setting_default	Initial command value used when the build setting is not overridden.	String	required

This rule is a specialized case of verilog_rtl_library. Systemverilog packages should be placed into their own rule instance to limit cross dependencies. In general, a block may depend on another block's package but should not need to depend on all the modules in the block.

PARAMETERS

Name	Description	Default Value
name	A unique name for this target.	none
direct	The Systemverilog file containing the package. See verilog_rtl_library::direct.	none
no_synth	Compatibility marker for downstream synthesis aspects or consumers. Simulation targets continue to include this package.	`False`
deps	Other packages this target is dependent on. See verilog_rtl_library::deps.	`[]`
visibility	Bazel target visibility.	`None`

verilog_rtl_shell

verilog_rtl_shell(name, module_to_shell_name, shell_module_label, deps, visibility)

An RTL shell has the same ports as another module.

This rule is a specialized case of verilog_rtl_library. A 'shell' is similar to a 'stub' (empty module), but a shell may contain limited functionality. Frequent uses include:

Blackboxing hierarchy that will not be the target of testing
Replacing functionality with a simpler model (e.g. simulation-only memory models)

PARAMETERS

Name	Description	Default Value
name	A unique name for this target.	none
module_to_shell_name	The name of the module that will be replaced. When a downstream test uses this 'shell', a gumi define will be created using this name. When a shell needs to be hand-edited after generation If module_to_shell_name == 'custom', then all rules regarding shells are ignored and gumi shell defines are not thrown, allowing the user great power.	none
shell_module_label	The Label or file containing the shell. The shell is selected explicitly by simulation consumers.	none
deps	Other packages this target is dependent on. In general. shells should avoid having dependencies. Exceptions include necessary packages and possible a DV model to implement functional behavior. See verilog_rtl_library::deps.	`[]`
visibility	Bazel target visibility forwarded to the generated `verilog_rtl_library`.	`None`