Testing custom IP cores

You can test your VHDL source files in Xilinx Vivado by running behavioral simulation. First of all, you have to make a VHDL test bench to test your IP. Hastlayer IP testbenches can be found at Hastlayer.ip\Test\src\vhd
In the testbench you need to instantiate the module you want to test, and to drive it's ports with pulses. In Test_Hast_IP.vhd there are a Counter, a BlockRAM, and the Hast_IP instantiated. A Moore State Machine controls the operation. First the BRAM is filled with test data generated by the counter.

When the BRAM is filled, the State Machine sets the Hast_IP's \Started\ port to '1', so the Hast_IP's State Machine starts to work.

To see the waveforms, do the following steps in Xilinx Vivado:

• In Vivado Flow Navigator click on Open Block Design.
• Right click on the Hast_IP peripheral, choose Edit in IP Packager. A new Vivado window will open.
• Right click in the new Vivado window Sources/Simulation Sources, and choose Edit Simulation Sets.
• Click on Add Sources (green "+" sign), and select Test_Hast_IP.vhd, Counter.vhd, Simple_DualPort_BRAM.vhd and Test_Hast_IP_behav.wcfg from Hastlayer.ip\Test\src\vhd. Test_Hast_IP_behav.wcfg is the waveform file.
• Now under Simulation Sources Test_Hast_IP - Imp will appear. Right click on it, choose Set as Top. This way you testbench will be your top module in the simulation.
• Now Right click on sim_1 (under Simulation Sources), and choose Run Simulation/Run Behavioral Simulation. A new waveform will be seen.
• Click on File menu/Open Waveform Configuration. Choose Test_Hast_IP_behav.wcfg. If you don't want to add this waveform to the simulation by every modification, save the waveform configuration in File menu, and when Vivado asks for adding this wcfg file to the simulation choose yes.
• Type restart in the TCL console. This will clear your waveform window.
• Type run x us. This will run the simulation for x us.

Note: after you are satisfied with the simulation results, save the modified files to a safe place, and repull the design from the version control system. Then overwrite the files which should be modified, and compile the design. Otherwise you can get errors during bitstream generation.