Vitis HLS Performance Pragma

August 4, 2026 · View on GitHub

This repository contains a curated collection of HLS (High-Level Synthesis) benchmarks drawn from AMD's open-source Vitis accelerated libraries. They are used to measure and validate the performance impact of Vitis HLS pragmas and optimizations.

Repository Structure

.
├── benchmark_1/           # Primary benchmark suite (multi-library collection)
│   ├── utils/             # AXI stream utilities and cache primitives
│   ├── xf_blas/           # BLAS (Basic Linear Algebra Subprograms) kernels
│   ├── xf_codec/          # JPEG decoder
│   ├── xf_compression/    # Data compression (LZ4, Snappy, CRC, Adler32)
│   ├── xf_DataAnalytics/  # Data analytics (SVM predict, etc.)
│   ├── xf_dsp/            # DSP kernels
│   ├── xf_fintech/        # Quantitative finance kernels
│   ├── xf_genomics/       # Genomics kernels
│   ├── xf_hpc/            # High-performance computing kernels
│   ├── xf_opencv/         # Computer vision (OpenCV) kernels
│   ├── xf_security/       # Security / cryptography kernels
│   └── xf_sparse/         # Sparse linear algebra kernels
├── utils/                 # Shared utility headers (AXI stream, cache, etc.)
├── xf_blas/               # Standalone BLAS benchmark suite
├── xf_compression/        # Standalone compression benchmark suite
├── xf_DataAnalytics/      # Standalone data analytics benchmark suite
├── xf_database/           # Database acceleration kernels
├── xf_fintech/            # Standalone quantitative finance benchmark suite
├── xf_graph/              # Graph analytics kernels
├── xf_opencv/             # Standalone OpenCV benchmark suite
├── xf_security/           # Standalone security benchmark suite
└── xf_solver/             # Linear algebra solver kernels (POTRF, etc.)

Each benchmark test directory typically contains:

File	Purpose
`hls_config.cfg`	Vitis HLS component configuration (part, clock, top function)
`run_hls.tcl`	TCL script to drive HLS flow (csim, csynth, cosim)
`description.json`	Test metadata (name, platform allowlist, timing targets)
`testinfo.yml`	CI test configuration
`.cpp` / `.hpp`	Kernel and testbench source files

Running a Benchmark

Using the top-level Makefile

# Run all tests (csim + csynth + cosim) for the u200 platform
make run DEVICE=u200 CSIM=1 CSYNTH=1 COSIM=1

# Run for a specific FPGA part
make run XPART=xcvu9p-flga2104-2-i CSYNTH=1

Running a single test directly

cd xf_compression/L1/tests/lz4_compress
make run DEVICE=u200 CSYNTH=1

Or invoke HLS directly:

cd xf_compression/L1/tests/lz4_compress
vitis-run --mode hls --tcl run_hls.tcl

Source Libraries

These benchmarks are derived from the following AMD Vitis open-source libraries:

Library	GitHub
Vitis BLAS	https://github.com/Xilinx/Vitis_Libraries/tree/main/blas
Vitis Compression	https://github.com/Xilinx/Vitis_Libraries/tree/main/data_compression
Vitis Data Analytics	https://github.com/Xilinx/Vitis_Libraries/tree/main/data_analytics
Vitis Database	https://github.com/Xilinx/Vitis_Libraries/tree/main/database
Vitis DSP	https://github.com/Xilinx/Vitis_Libraries/tree/main/dsp
Vitis Fintech	https://github.com/Xilinx/Vitis_Libraries/tree/main/quantitative_finance
Vitis Graph	https://github.com/Xilinx/Vitis_Libraries/tree/main/graph
Vitis OpenCV	https://github.com/Xilinx/Vitis_Libraries/tree/main/vision
Vitis Security	https://github.com/Xilinx/Vitis_Libraries/tree/main/security
Vitis Solver	https://github.com/Xilinx/Vitis_Libraries/tree/main/solver

Repository Structure

Running a Benchmark

Using the top-level Makefile

Running a single test directly

Source Libraries

License