RISC-V based Microprocessor using TL-Verilog

October 26, 2020 ยท View on GitHub

This repository contains information and code that was formed during the RISC-V MYTH Workshop. A RISC-V pipelined core that supports RV32I base integer instructions was developed on Makerchip and written in TL-Verilog.

Table of Contents

Day 1

Introduction to RISC-V ISA

RISC-V is an open standard instruction set architecture (ISA), meaning it is provided under open source licenses and available to the public. It is comprised of a base integer ISA (RV32I/RV64I) with optional extension ISAs and belongs to the little endian memory addressing system.

GNU Compiler Toolchain

The GNU compiler toolchain is a collection of programming tools used for developing applications and operating systems; it has tools that make and compile code into machine-readable programs. The flow from user to machine code is as follows:

  1. Preprocessor: process user code to be read by compiler such as macro expansion and file inclusion.
  2. Compiler: compile source code to assembly instructions
  3. Assembler: convert assembly to relocatable machine code
  4. Linker: converts assembler output to absolute machine code

RISC-V Toolchain

Compile command:

$ riscv64-unkown-elf-gcc -O<1/fast> -mabi=lp<XLEN> -march=rv<XLEN>i -o <output_program> <input_user_file> [<input_user_file>...]

Assembly preview command:

$ riscv64-unkown-elf-objdump -d <output_program>

Run command:

$ spike pk <output_program>

Debug command:

$ spike -d pk <output_program>

Day 2

Application Binary Interface (ABI)

The Application Binary Interface (ABI), also known as the System Call Interface, is used by the program to access the ISA registers. RISC-V architecture contains 32 registers of width 32/64 if using RV32I/RV64I, respectively:

RegisterABI NameUsage
x0zeroHard-wired zero
x1raReturn address
x2spStack pointer
x3gpGlobal pointer
x4tpThread opinter
x5-7t0-2Temporaries
x8s0/fpSaved register/frame pointer
x9s1Saved register
x10-11a0-1Function arguments/return values
x12-17a2-7Function arguments
x18-27s2-11Saved registers
x28-31t3-6Temporaries

There are 3 types of instructions:

  1. R-type: operate only on registers
    Ex: add x8, x24, x8
  2. I-type: operate on registers and immediate values
    Ex: ld x8, 16(x23)
  3. S-type: operate on source registers and store in immediate value
    Ex: sd x8, 8(x23)

Day 2 Lab: ABI Function Calls

A simple program for summing numbers 1 to 9 was created; view source in Day2 folder. The compiled output in assembly looks like this:

day2_lab_assembly

Day 3

TL-Verilog and Makerchip

Transaction-Level Verilog (TL-Verilog) is a hardware descriptive language (HDL) that extends Verilog in the context of pipelines; specifically, it maintains behavior of the circuit while being timing abstract, which means it takes care of retiming.

Makerchip is a free online platform made by Redwood EDA. It supports TL-Verilog, SystemVerilog, and Verilog languages to code, compile, simulate, and debug digital designs.

Day 3 Lab: Calculator Single Value Memory Lab

A simple calculator with single value memory and validity was created; view source here. The diagram and viz showing one cycle of operation:

day3_lab_calculator

Day 4

RISC-V Microarchitecture

The building blocks of a simple CPU are program counter (PC), instruction memory (IMem Rd), instruction decoder (Dec), register file read (RF Rd), arithmetic logic unit (ALU), register file write (RF Wr), and data memory (DMem Rd/Wr). The following diagram depicts the connections between these blocks:

day4_riscv_block_diagram

Day 4 Lab: Simple RISC-V Core

A simple RISC-V core from fetch and decode to control logic with branching was created; view source here. The diagram and viz showing final instruction executed:

day4_lab_riscv_simple

Day 5

RISC-V Pipelining

Pipelining is used in designs to cut down the amount of combinational logic between flip-flops. This allows for higher clock speeds and, for a processor, more instructions per second (IPS). In order for this to function properly, the flow of logic must be broken up into pipe stages; the implemented RISC-V core's stages are seen in the below diagram:

day5_riscv_pipeline

This introduces hazards that were not seen before pipelining:

  • Control flow hazard
    • Hazard: branch and jump instructions update PC in stage @3 when it is needed in stage @1
    • Solution: invalidate the next 2 instructions
  • Read after write hazard
    • Hazard: register file read occurs before register file write on previous instruction (stage @4 versus @2)
    • Solution: for dependent instructions (write to register followed by read from same register), select previous instruction's ALU output data/register file write input data (write stage @3 is in parallel with read stage @2)
  • Load instruction redirect
    • Hazard: load data from memory is valid 2 cycles after register write (stage @5 versus @3)
    • Solution: invalidate the next 2 instructions and select load data for register file write data when it is valid

Day 5 Lab: Pipelined RISC-V Core

A RISC-V core that implements the ISA was pipelined; view source here.

RISC-V Core Block Diagram

The pipe stages are the green boxes and contain signals for that stage.

day5_lab_riscv_graph

Viz of Final Result being Stored/Loaded

The final summation result of 45 was stored in DMem (address 1) then loaded from DMem into r15/a5.

day5_lab_riscv_dmem

Resultant Verilog Comparison

SandPiper generated ~40,000 characters of SystemVerilog from ~10,000 characters of TL-Verilog (excluding whitespace, comments, and instrumentation).

day5_lab_riscv_compare

Future Work

The current state of this RISC-V core implements almost all of RV32I base instruction set. Future improvements include completing the remaining instructions in RV32I and adding instruction set extensions such as RV32M, RV32F, and RV32D.

References

A compiled list of references used during this workshop:

Acknowledgements

Contact Information