Verilog Doc

August 1, 2016 ยท View on GitHub

Documentation Build Status Coverage Status Licence: MIT

This project aims to provide a Doxygen-like tool for the Verilog Hardware Description Language (HDL).

It is currently under heavy development, and in the early stages of construction. None the less, it can parse input source trees and spit out a module hierarchy and file list, as well as document a modules ports.