The RISC-V Microcontroller Profile
February 15, 2022 ยท View on GitHub
A proposal for a friendlier microcontroller architecture using the RISC-V instruction set.
Version: 0.2.1-pre
Editors:
- Liviu Ionescu
Warning: This draft specification is in a preliminary phase and may change at any time. For the moment it is more like a wish list than a real specs document.
Motto
"People are more expensive than transistors".
Table of Contents
- Introduction
- Memory Map
- The Startup Process
- Exceptions and Interrupts
- Control and Status Registers (CSRs)
- Hart Control Block (
hcb) - Hart Interrupt Controller (
hic) - Device Control Block (
dcb) - Device Real-Time Clock (
rtclock) - Device System Clock (
sysclock) - Device Watchdog Timer (
wdog) - Embedded ABI (EABI)
- RTOS Support Features
- Appendix A: Improvements upon RISC-V privileged <--- Read Me First!
- Appendix B: Interrupts use cases
- Appendix C: History
- Appendix D: Contributing
TODO:
- add MPU definitions
- add more details about the restrictions in user mode.
License
This document is released under a Creative Commons Attribution 4.0 International license.