A technical Markdown specification for emulating the MOS Technology 6502 CPU family, suitable for software emulators, educational tools, testing frameworks, and retrocomputing projects.
This specification describes the functional requirements for emulating:
- MOS 6502
- WDC 65C02 (where noted)
Out of scope:
- Cycle-exact analog behavior
- Physical bus contention
- Undocumented silicon defects (unless explicitly implemented)
| Feature | Value |
|---|
| Data width | 8-bit |
| Address width | 16-bit |
| Address space | 64 KB |
| Endianness | Little-endian |
| Clock | Single-phase |
| Register | Size | Description |
|---|
| A | 8-bit | Accumulator |
| X | 8-bit | Index register |
| Y | 8-bit | Index register |
| SP | 8-bit | Stack pointer (page $01xx) |
| PC | 16-bit | Program counter |
| P | 8-bit | Processor status flags |
| Bit | Name | Meaning |
|---|
| 7 | N | Negative |
| 6 | V | Overflow |
| 5 | - | Unused (always 1 when pushed) |
| 4 | B | Break |
| 3 | D | Decimal |
| 2 | I | IRQ disable |
| 1 | Z | Zero |
| 0 | C | Carry |
- 16-bit address bus (
$0000-$FFFF)
- Byte-addressable
read(address) -> byte
write(address, byte)
- Stack base:
$0100
- Push:
write(\$0100 + SP, value); SP--
- Pull:
SP++; value = read(\$0100 + SP)
- Set
I = 1
- Set
SP = $FD
- Clear
D
- Load
PC from $FFFC-$FFFD
| Interrupt | Vector Address |
|---|
| NMI | $FFFA-$FFFB |
| RESET | $FFFC-$FFFD |
| IRQ/BRK | $FFFE-$FFFF |
opcode = read(PC++)
decode opcode
fetch operands
execute instruction
update flags
increment cycles
| Mode | Example | Notes |
|---|
| Immediate | LDA #\$10 | Constant |
| Zero Page | LDA \$20 | Wraps at $00FF |
| Absolute | LDA \$2000 | Full address |
| Indexed | LDA \$2000,X | Optional page penalty |
| Indirect | JMP ($FFFC) | Page wrap bug |
| Indexed Indirect | LDA (\$20,X) | ZP indexed |
| Indirect Indexed | LDA (\$20),Y | ZP pointer |
- Load/Store
- Arithmetic (ADC, SBC)
- Logic (AND, ORA, EOR)
- Shifts & Rotates
- Branches
- Stack operations
- System control
- Applies to
ADC and SBC
- Uses BCD arithmetic when
D = 1
| Instruction Type | Flags Affected |
|---|
| Loads | N, Z |
| ADC/SBC | N, V, Z, C |
| CMP/CPX/CPY | N, Z, C |
| INC/DEC | N, Z |
| Shifts | N, Z, C |
| Level | Description |
|---|
| Functional | Correct results only |
| Instruction-accurate | Fixed cycle counts |
| Cycle-accurate | Page-cross penalties |
- Branch taken: +1 cycle
- Branch crosses page: +2 cycles
- Indexed load crosses page: +1 cycle
| Quirk | Description |
|---|
| JMP indirect bug | High byte wrap at page boundary |
| BRK sets B flag | Only when pushed |
| Unused flag bit | Always reads as 1 |
- Many opcodes perform composite operations
- Behavior varies by silicon revision
- Should be disabled or explicitly enabled
- One instruction executed per multiple clock cycles
- Emulator may execute instructions per host tick
- Cycle counter required for I/O timing
if address in IO range:
delegate to device
Examples:
- 6522 VIA
- UART
- Video hardware
- Klaus Dormann 6502 functional tests
- Interrupt and decimal mode tests
- All instructions execute correctly
- Flags match reference behavior
- Vectors handled properly
- Stack operations correct
Document Scope: Software emulation of the 6502 CPU
Audience: Emulator developers, retrocomputing engineers
Status: Stable technical reference