A high-level introduction of microarchitectural overview is available as a tech report.

Details about the microarchitecture are available here.

Features

Feature	Description
Instruction set	RV64IMAC (FD support optional)
Privilege modes	M/S/U
Virtual addressing modes	Sv39
Interrupt modes	Direct
Physical memory protection	Not supported
Debug mode	Not supported
Unaligned loads/stores	Not supported

Standards

The Muntjac processor meets the following standards:

Standard	Version
RV64I: Base Integer Instruction Set, 64-bit	2.1
M: Standard Extension for Integer Multiplication and Division	2.0
A: Standard Extension for Atomic Instructions	2.1
C: Standard Extension for Compressed Instructions	2.0
ZiCSR: Control and Status Register (CSR)	2.0
Zifencei: Instruction-Fetch Fence	2.0
Machine ISA	1.11
Supervisor ISA	1.11

Much of the content in the RISC-V Privileged Specification (i.e. the machine and supervisor ISAs) is optional. The features supported by Muntjac are detailed here.