ruapu
May 22, 2026 · View on GitHub
Detect CPU ISA features with single-file
| CPU | ✅ x86, x86-64 ✅ arm, aarch64 ✅ mips ✅ powerpc ✅ s390x ✅ loongarch ✅ risc-v ✅ openrisc |
|
| OS | ✅ Windows ✅ Linux ✅ macOS ✅ Android ✅ iOS ✅ FreeBSD ✅ NetBSD ✅ OpenBSD ✅ DragonflyBSD ✅ Solaris ✅ SyterKit | |
| Compiler | ✅ GCC ✅ Clang ✅ MSVC ✅ MinGW |
Best practice for using ruapu.h in multiple compilation units
- Create one
ruapu.cfor your project ruapu.cis ONLY#define RUAPU_IMPLEMENTATIONand#include "ruapu.h"- Other sources
#include "ruapu.h"but NO#define RUAPU_IMPLEMENTATION
Features
- Detect CPU ISA with single-file
sse2,avx,avx512f,neon, etc. - Detect vendor extended ISA
apple
amx, risc-v vendor ISA, etc. - Detect richer ISA on Windows ARM
IsProcessorFeaturePresent()returns little ISA information - Detect
x86-avx512on macOS correctly macOS hides it incpuid - Detect new CPU's ISA on old systems
they are usually not exposed in
auxvorMISA - Detect CPU hidden ISA
fma4on zen1, ISA in hypervisor, etc.
Supported ISA (more is comming ... :)
| CPU | ISA |
|---|---|
| x86 | mmx sse sse2 sse3 ssse3 sse41 sse42 sse4a popcnt xop avx f16c fma fma4 avx2 avx512f avx512bw avx512cd avx512dq avx512vl avx512vnni avx512bf16 avx512ifma avx512vbmi avx512vbmi2 avx512fp16 avx512er avx5124fmaps avx5124vnniw avxvnni avxvnniint8 avxvnniint16 avxifma avxneconvert amxfp16 amxbf16 amxint8 amxtile bmi1 bmi2 gfni aesni vaes sha1 sha256 sha512 sm3 sm4 rdrand rdseed tsx |
| arm | half edsp neon vfpv4 idiv |
| aarch64 | neon vfpv4 lse cpuid asimdrdm asimdhp asimddp asimdfhm bf16 i8mm frint jscvt fcma mte mte2 sve sve2 sve2p1 svebf16 svei8mm svef32mm svef64mm sme smef16f16 smef64f64 smei64i64 pmull crc32 aes sha1 sha2 sha3 sha512 sm3 sm4 svepmull svebitperm sveaes svesha3 svesm4 amx paca pacg |
| mips | msa mmi sx asx msa2 crypto |
| powerpc | altivec vsx |
| s390x | zvector |
| loongarch | lsx lasx |
| risc-v | i m a f d c p v zawrs zba zbb zbc zbpbo zbs zbkb zbkc zbkx zcb zfa zfbfmin zfh zfhmin zicbop zicbom zicond zicsr zifencei zihintpause zmmul zpn zpsfoperand zvbb zvbc zvfh zvfhmin zvfbfmin zvfbfwma zvkb zvkg zvkned zvknha zvknhb zvksed zvksh zvl32b zvl64b zvl128b zvl256b zvl512b zvl1024b xsfvfnrclipxfqf xsfvfwmaccqqq xsfvqmaccdod xsfvqmaccqoq xtheadba xtheadbb xtheadbs xtheadcondmov xtheadfmemidx xtheadfmv xtheadmac xtheadmemidx xtheadmempair xtheadsync xtheadvector xtheadvdot xsmtvmadoti8 xsmtvmadoti4 xsmtvmadotni8 xsmtvfmadotf32 xsmtvfwmadotf16 xsmtvmadothpi8 xsmtvmadothpi4 xsmtvpack xsmtvnspack |
| openrisc | orbis32 orbis64 orfpx32 orfpx64 orvdx64 |
Let's ruapu
ruapu with C
|
Compile ruapu test program
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Run ruapu in command line
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ruapu with Python
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Compile and install ruapu library
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Use ruapu in python
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ruapu with Rust
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Compile ruapu library
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Use ruapu in Rust
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ruapu with Lua
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Compile ruapu library
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Use ruapu in Lua
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ruapu with Erlang
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Compile ruapu library
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Use ruapu in Erlang
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ruapu with Fortran
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Compile ruapu library
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Use ruapu in Fortran
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ruapu with Golang
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Compile ruapu library
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Use ruapu in Golang
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ruapu with Haskell
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Add ruapu library to your project
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Use ruapu in Haskell
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ruapu with Vlang
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Compile ruapu library
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Use ruapu in Vlang
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ruapu with Pascal
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Compile ruapu library
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Use ruapu in Pascal
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ruapu with Java
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Compile ruapu library and example
Run example
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Use ruapu in Java
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ruapu with cangjie
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Compile ruapu library
run example
or compile example
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Use ruapu in cangjie
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ruapu with Dart
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Compile ruapu library
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Use ruapu in dart
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Github-hosted runner result (Linux)
mmx = 1
sse = 1
sse2 = 1
sse3 = 1
ssse3 = 1
sse41 = 1
sse42 = 1
sse4a = 1
xop = 0
avx = 1
f16c = 1
fma = 1
avx2 = 1
avx512f = 0
avx512bw = 0
avx512cd = 0
avx512dq = 0
avx512vl = 0
avx512vnni = 0
avx512bf16 = 0
avx512ifma = 0
avx512vbmi = 0
avx512vbmi2 = 0
avx512fp16 = 0
avx512er = 0
avx5124fmaps = 0
avx5124vnniw = 0
avxvnni = 0
avxvnniint8 = 0
avxifma = 0
amxfp16 = 0
amxbf16 = 0
amxint8 = 0
amxtile = 0
Github-hosted runner result (macOS)
mmx = 1
sse = 1
sse2 = 1
sse3 = 1
ssse3 = 1
sse41 = 1
sse42 = 1
sse4a = 0
xop = 0
avx = 1
f16c = 1
fma = 1
avx2 = 1
avx512f = 0
avx512bw = 0
avx512cd = 0
avx512dq = 0
avx512vl = 0
avx512vnni = 0
avx512bf16 = 0
avx512ifma = 0
avx512vbmi = 0
avx512vbmi2 = 0
avx512fp16 = 0
avx512er = 0
avx5124fmaps = 0
avx5124vnniw = 0
avxvnni = 0
avxvnniint8 = 0
avxifma = 0
amxfp16 = 0
amxbf16 = 0
amxint8 = 0
amxtile = 0
Github-hosted runner result (macOS M1)
neon = 1
vfpv4 = 1
cpuid = 0
asimdhp = 1
asimddp = 1
asimdfhm = 1
bf16 = 0
i8mm = 0
sve = 0
sve2 = 0
svebf16 = 0
svei8mm = 0
svef32mm = 0
Github-hosted runner result (Windows)
mmx = 1
sse = 1
sse2 = 1
sse3 = 1
ssse3 = 1
sse41 = 1
sse42 = 1
sse4a = 1
xop = 0
avx = 1
f16c = 1
fma = 1
avx2 = 1
avx512f = 0
avx512bw = 0
avx512cd = 0
avx512dq = 0
avx512vl = 0
avx512vnni = 0
avx512bf16 = 0
avx512ifma = 0
avx512vbmi = 0
avx512vbmi2 = 0
avx512fp16 = 0
avx512er = 0
avx5124fmaps = 0
avx5124vnniw = 0
avxvnni = 0
avxvnniint8 = 0
avxifma = 0
amxfp16 = 0
amxbf16 = 0
amxint8 = 0
amxtile = 0
FreeBSD/NetBSD/OpenBSD VM result (x86_64)
mmx = 1
sse = 1
sse2 = 1
sse3 = 1
ssse3 = 1
sse41 = 1
sse42 = 1
sse4a = 1
xop = 0
avx = 1
f16c = 1
fma = 1
fma4 = 0
avx2 = 1
avx512f = 0
avx512bw = 0
avx512cd = 0
avx512dq = 0
avx512vl = 0
avx512vnni = 0
avx512bf16 = 0
avx512ifma = 0
avx512vbmi = 0
avx512vbmi2 = 0
avx512fp16 = 0
avx512er = 0
avx5124fmaps = 0
avx5124vnniw = 0
avxvnni = 0
avxvnniint8 = 0
avxifma = 0
amxfp16 = 0
amxbf16 = 0
amxint8 = 0
amxtile = 0
Techniques inside ruapu
ruapu is implemented in C language to ensure the widest possible portability.
ruapu determines whether the CPU supports certain instruction sets by trying to execute instructions and detecting whether an Illegal Instruction exception occurs. ruapu does not rely on the cpuid instructions and registers related to the CPU architecture, nor does it rely on the MISA information and system calls of the operating system. This can help us get more detailed CPU ISA information.
FAQ
Why is the project named ruapu
ruapu is the abbreviation of rua-cpu, which means using various extended instructions to harass and amuse the CPU (rua!). Based on whether the CPU reacts violently (throws an illegal instruction exception), it is inferred whether the CPU supports a certain extended instruction set.
Why is ruapu API designed like this
We consider gcc builtin functions to be good practice, saying __builtin_cpu_init() and __builtin_cpu_supports(). ruapu refers to this design, which can be a 1:1 replacement for gcc functions, and supports more operating systems and compilers, giving it better portability.
Why does SIGILL occur when executing in debugger or simulator, such as gdb, lldb, qemu-user, sde etc.
Because debuggers and simulators capture the signal and stop the ruapu signal handler function by default, we can continue execution at this time, or configure it specifically, such as handle SIGILL nostop in gdb. ruapu technically cannot prevent programs from stopping in debuggers and emulators
How to add detection capabilities for new instructions to ruapu
Assume that the new extended instruction set is named rua
- Add
RUAPU_INSTCODE(rua, rua-inst-hex) // rua r0,r0andRUAPU_ISAENTRY(rua)inruapu.h - Add
PRINT_ISA_SUPPORT(rua)inmain.cto print the detection result - Add entries about
ruain README.md - Create a pull request!
https://godbolt.org/ is a good helper to view the compiled binary code of instructions.
Repos that use ruapu
- ncnn High-performance neural network inference framework
- libllm Efficient inference of large language models
Credits
Contribution behavior
- @nihui Write the initial POC code and ruapu maintainer
- @kernelbin Implement exception handling for Windows
- @zchrissirhcz Detect x86 FMA4
- @MollySophia Fix C++ export symbol
- @strongtz Detect more aarch64 ISA
- @monkeyking Detect apple arm64 AMX
- @junchao-loongson Add loongarch support
- @ziyao233 Detect more risc-v ISA, add Lua and Haskell binding
- @dreamcmi Detect more risc-v ISA
- @cocoa-xu Add FreeBSD support, python support
- @YuzukiTsuru Add OpenRISC support
- @whyb Detect more x86 AMX*, SHA*, AVX512*, SM*
- @Yoh-Z Enhance python API
- @mizu-bai Add Fortran binding
- @scarsty Add Pascal binding
- @LJoson Add contributor image
- @Deepdive543443 Add Java binding
- @synodriver Improve python binding
- @dtcxzyw Detect more risc-v ISA
- @TianZerL Fix Windows DLL crashes, UWP support
- @cyyself Detect risc-v zmmul
- @AlexHJH Detect risc-v spacemit vmadot
- @eastonman Detect risc-v zcb
- @Apachiww Detect x86 aes-ni, sha, bmi, gfni, vaes, rdrand, rdseed, tsx
- @clingfei Detect arm64 paca and pacg
- @bakacai Add Cangjie binding
- @windowsair Remove windows.h dependency
- @alex-spacemit Detect risc-v xsmt ime2
- @Integral-Tech Detect x86 popcnt
License
MIT License