FPGA flow

May 21, 2025 ยท View on GitHub

Installation and Overview of SandPiper

  • SandPiper is a code generator that generates readable, well-structured, Verilog or SystemVerilog\ code from the given TL-Verilog code.
  • SandPiper SaaS Edition runs as a microservice in the cloud to support easy open-source development. Install Sanpiper SaaS Edition for this project.

Steps to run FPGA setup

  1. git clone https://github.com/os-fpga/Virtual-FPGA-Lab.git

  2. From your working directory run the shell script /<complete_path>/run.sh. image

  3. Three inputs will be asked by shell script

    a. Input file name of TL-Verilog file

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    b. Board name (if board is not from given options then provide part number of board)

    If board is from given options:

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    If board is not from given options:

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    c. (Optional) If board is not from given options then constraints file should be present in your working directory as <filename_partno>.xdc.

    For example: From above iamge it should be design_xc7a100tcsg324-1.xdc

    d. Clock period (in ns)

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