meta-riscv

June 23, 2026 · View on GitHub

RISC-V Architecture Layer for OpenEmbedded/Yocto

Description

This is the general hardware-specific BSP overlay for the RISC-V based devices.

More information can be found at: https://riscv.org/ (Official Site)

The core BSP part of meta-riscv should work with different OpenEmbedded/Yocto distributions and layer stacks, such as:

For details regarding basic usage for some platforms supported by this layer, see the Quick Start Guide.

This layer depends on:

MACHINE	Platform	Notes
bananapi-f3	BPI-F3	Mainline Kernel and U-Boot (uses vendor FSBL)
bananapi-cm6-io	BPI-CM6	Mainline Kernel and U-Boot (uses vendor FSBL)
beaglev-ahead	BeagleV-Ahead
beaglev-starlight-jh7100	BeagleV	No longer produced
dc-roma-fml13v01	DC-ROMA RISC-V Mainboard	Upstream mainline kernel (7.0) with the in-tree `jh7110-deepcomputing-fml13v01` DTS, Framework Laptop 13 compatible mainboard
eswin-ebc77	ESWIN EBC77	Vendor kernel. Use `eswin-ebc77-mainline` for upstream version
eswin-ebc77-mainline	ESWIN EBC77
k3-pico-itx	Sipeed K3 Pico-ITX	Vendor Kernel
freedom-u540	HiFive Unleashed	Discontinued
mangopi-mq-pro	MangoPi MQ Pro
milkv-duo	Milk-V Duo
milkv-megrez	Milk-V Megrez	Build broken due to downstream kernel commit since being branchless
muse-pi-pro	Muse Pi Pro
nezha-allwinner-d1	Nezha D1-H
orangepi-r2s	OrangePi R2S	Vendor Kernel and U-Boot
orangepi-rv2	OrangePi RV2	Vendor Kernel and U-Boot
orangepi-rv2-mainline	OrangePi RV2	Mainline Kernel and U-Boot (uses vendor FSBL)
star64	PINE64 STAR64	5.15 Kernel fork
visionfive	StarFive VisionFive	No product page found
visionfive2	StarFive VisionFive 2

Note that this layer also provides improvements and features for the upstream qemuriscv32 and qemuriscv64 machines.

Submit patches via GitHub pull requests, Use GitHub issues to report problems or to send comments.