Design ∪ Hardware

DUH ("Spirit" in most slavic languages. pronounced /dûx/, with the final consonant of loch or Bach) is a suite of tools for packaging reusable hardware components and designs. DUH enables the generation of JSON5 (duh documents) for describing these components, and also enables export from these documents to output deliverables.

Install

duh requires Node.js (versions 22, 24, 26). Check your version:

node --version

See Installing Node.js via package manager.

Install duh tool suite globally:

npm i -g duh

Or install it locally and add ./node_modules/.bin/ to your PATH.

In Bash:

export PATH=./node_modules/.bin:$PATH

Test the installation with duh --help.

Quick start

Base set of DUH tools to author duh documents:

• Create

  • Run duh init to interactively scaffold a base document.

• Import

  • Verilog: pipe RTL into duh import verilog to import the ports of the module whose name matches component.name.
  • Verilog (simple): duh import verilog-simple imports every pin found in the source, without module-name matching.
  • IPXACT: duh-ipxact

• Infer

  • Run duh infer channels to infer channel bus interfaces from ports named with _vld / _rdy / _dat suffixes.

• Validate

  • Run duh validate to test whether a given document conforms to the DUH document structure.

• Export

  • Run duh export bbx to generate a Verilog black-box wrapper for the component.
  • Scala / Chisel: duh-scala
  • IPXACT: duh-ipxact

Commands

As of 2.0, all functionality lives under a single duh command:

duh init [filename]                        # scaffold a new document (interactive)
duh validate <filename>                    # validate against the DUH schema (alias: val)
duh get <value> [filename]                 # print a value at a path within the document

duh import verilog [filename] [-i rtl.v] [-o out.json5]         # ports of module == component.name
duh import verilog-simple [filename] [-i rtl.v] [-o out.json5]  # every pin, no module matching

duh infer channels [filename] [-o out.json5]   # channel bus interfaces from _vld/_rdy/_dat ports

duh export bbx [filename] [-o outdir]      # Verilog black-box wrapper
duh export header [filename] [-o outdir]   # C header file

When filename (the duh document) is omitted, commands default to <current-folder>.json5. Verilog import reads RTL from -i / --input, or from stdin when no file is given. import and infer write back to the input document unless -o / --output is set (a warning is printed when overwriting in place).

Migration from 1.x

The standalone bins were merged into duh subcommands:

1.x	2.0
duh-import-verilog-ports	duh import verilog
duh-import-verilog-ports-simple	duh import verilog-simple
duh-infer-channels	duh infer channels
duh-export-verilog-bbx	duh export bbx

DUH toolbox

• duh-scala -- Scala / Chisel export
• duh-ipxact -- IP-XACT import / export
• duh-systemrdl -- SystemRDL import / export
• duh-bus -- DUH Bus Definitions
• duh-schema -- DUH document JSON schema
• duh-core -- DUH core library
• duh-verilog -- Verilog generator from DUH document
• duh-svd -- DUH to SVD converter

Example of DUH documents

• block-ark for a walk-through example using the DUH suite on a standalone module to produce a valid duh-document that fully describes the mapping of ports to known bus definitions.