Exemplary NEORV32 Setups and Projects

June 21, 2026 ยท View on GitHub

Containers Implementation License

This repository provides community projects as well as exemplary setups for different FPGAs, platforms, boards and toolchains for the NEORV32 RISC-V Processor. Project maintainers may make pull requests against this repository to add or link their setups and projects.

Tip

Ready-to-use bitstreams for the provided open source toolchain-based setups are available via the assets of theImplementation Workflow.

Community Projects

This list shows projects that focus on custom hard- or software modifications, specific applications, etc.

LinkDescriptionAuthor(s)
:earth_africa: RISC-V LabRISC-V student lab by Fraunhofer IMS and University of Duisburg-EssenFraunhofer IMS
:earth_africa: github.com/motiustutorial: custom CRC32 processor module for the nexys-a7 boardsmotius (ikstvn, turbinenreiter)
:earth_africa: neorv32-examplesNEORV32 setups/projects for different Intel/Terasic boardsemb4fun
:earth_africa: neorv32-xmodem-bootloaderA XModem Bootloader for the DE0-Nano boardemb4fun
:earth_africa: neorv32-xip-bootloaderA XIP (eXecute In Place) Bootloader for the NEORV32betocool-prog
:earth_africa: FPGA-Based AI Accelerator with NEORV32 CFSCustom FPGA-based neural network inference accelerator integrated with the NEORV32 RISC-V soft-core via the Custom Functions Subsystem (CFS).Abdulrahman Ghaleb

Setups using Commercial Toolchains

The setups using commercial toolchains provide pre-configured project files that can be opened with the according FPGA tools.

SetupToolchainBoardFPGAAuthor(s)
:file_folder: de0-nano-test-setupIntel Quartus PrimeTerasic DE0-NanoIntel Cyclone IV EP4CE22F17C6Nstnolting
:file_folder: de10-nano-test-setupIntel Quartus PrimeTerasic DE10-NanoIntel Cyclone V 5CSEBA6U23I7provoostkris
:file_folder: de0-nano-test-setup-qsysIntel Quartus PrimeTerasic DE0-NanoIntel Cyclone IV EP4CE22F17C6Ntorerams
:file_folder: de0-nano-test-setup-avalonmmIntel Quartus PrimeTerasic DE0-NanoIntel Cyclone IV EP4CE22F17C6Ntorerams
:file_folder: terasic-cyclone-V-gx-starter-kit-test-setupIntel Quartus PrimeTerasic Cyclone-V GX Starter KitIntel Cyclone V 5CGXFC5C6F27C7Nzs6mue
:file_folder: UPduino_v3Lattice RadianttinyVision.ai Inc. UPduino v3.0Lattice iCE40 UltraPlus iCE40UP5K-SG48Istnolting
:file_folder: iCEBreakerLattice RadiantiCEBreaker @ GitHubLattice iCE40 UltraPlus iCE40UP5K-SG48Istnolting
:file_folder: arty-a7-35-test-setupXilinx VivadoDigilent Arty A7-35Xilinx Artix-7 XC7A35TICSG324-1Lstnolting
:file_folder: nexys-a7-test-setupXilinx VivadoDigilent Nexys A7Xilinx Artix-7 XC7A50TCSG324-1AWenzel83
:file_folder: nexys-a7-test-setupXilinx VivadoDigilent Nexys 4 DDRXilinx Artix-7 XC7A100TCSG324-1AWenzel83
:file_folder: z7-nano-test-setupXilinx VivadoMicrophase Z7 Nano FPGA BoardXilinx ZynQ 7000 c7z020clg400-2provoostkris
:file_folder: cora-z7-test-setupXilinx VivadoDigilent Cora Z7Xilinx ZynQ 7000 xc7z007sclg400-1eivindbergem
:file_folder: on-chip-debugger-alteraAltera Quartus PrimeGecko4EducationAltera Cyclone IV E EP4CE15F23C8NikLeberg
:file_folder: tang-nano-9kGowin EDASipeed Tang Nano 9KGowin LittleBee GW1NR-9 GW1NR-LV9QN88PC6/I5IvanVeloz
:file_folder: tang-nano-20kGowin EDASipeed Tang Nano 20KGowin Morningside GW2A-18 GW2AR-LV18QN88C8/I7duvitech-llc

Setups using Open-Source Toolchains

Most OSS setups using open-source toolchains are located in the osflow folder. See the README there for more information how to run a specific setup and how to add new targets.

SetupToolchainBoardFPGAAuthor(s)
:file_folder: UPDuino-v3.0GHDL, Yosys, nextPNRUPduino v3.0Lattice iCE40 UltraPlus iCE40UP5K-SG48Itmeissner
:file_folder: FOMUGHDL, Yosys, nextPNRFOMULattice iCE40 UltraPlus iCE40UP5K-SG48Iumarcor
:file_folder: iCESugarGHDL, Yosys, nextPNRiCESugarLattice iCE40 UltraPlus iCE40UP5K-SG48Iumarcor
:file_folder: AlhambraIIGHDL, Yosys, nextPNRAlhambraIILattice iCE40HX4Kzipotron
:file_folder: Orange CrabGHDL, Yosys, nextPNROrange CrabLattice ECP5-25Fumarcor, jeremyherbert
:file_folder: ULX3SGHDL, Yosys, nextPNRULX3SLattice ECP5 LFE5U-85F-6BG381Czipotron
:file_folder: GateMateA1-EVBGHDL, Yosys, CC P_RGateMateA1-EVB(-2M)Cologne Chip GateMate CCGM1A1stnolting
:file_folder: ChipWhisperer iCE40CW312GHDL, Yosys, nextPNRCW312T_ICE40UPLattice iCE40 UltraPlus iCE40UP5K-UWG30colinoflynn
:earth_africa: ULX3S-SDRAMGHDL, Yosys, nextPNRULX3SLattice ECP5 LFE5U-85F-6BG381Czipotron
:file_folder: TangNano20kGHDL, Yosys, nextPNRTang Nano 20KGOWIN GW2AR GW2AR-18 QN88d-orthofer

Adding Your Project or Setup

Please respect the following guidelines if you'd like to add or link your setup/project to the list:

  • check out the project's code of conduct
  • for FPGA- / board- / toolchain-specific setups:
    • a "setup" is a wrapped (and maybe script-aided) implementation of the NEORV32 processor for a certain FPGA/board/toolchain
    • add a link if the board you are using provides online documentation or can be purchased somewhere
    • use the :file_folder: emoji (:file_folder:) if the setup is located in this repository; use the :earth_africa: emoji (:earth_africa:) if it is a link to your local project
    • please add a README.md file to give some brief information about the setup and a .gitignore file to keep things clean
    • for local setups you can add your setup to the implementation GitHub actions workflow to automatically generate up-to-date bitstreams for your setup
  • for projects:
    • provide a link to your project (use the :earth_africa: (:earth_africa:) emoji)
    • provide a short description
    • further information should be provided by a project-local README

Setup-Specific NEORV32 Software Framework Modifications

In order to use the features provided by the setups, minor optional changes can be made to the default NEORV32 setup.