RISCOF / RISC-V Architecture Tests

May 20, 2026 ยท View on GitHub

RISCOF (RISC-V Compatibility Framework) is a Python-based framework that facilitates testing of a RISC-V target against a golden reference model.

The RISC-V Architectural Tests (riscv-arch-test) provide a fundamental set of tests that can be used to verify that the behavior of the RISC-V model aligns with RISC-V standards while executing specific applications. These tests are not meant to replace thorough design verification.

Reference signatures are generated by the formal RISC-V model RISC-V SAIL in Executable and Linkable Format (ELF) files. ELF files contain multiple testing instructions, data, and signatures, such as cadd-01.elf. The specific data locations that the testing model (this emulator) must write to during the test are referred to as test signatures. These test signatures are written upon completion of the test and are then compared to the reference signature. Successful tests are indicated by matching signatures.

Install RISCOF

To install RISCOF:

$ python3 -m pip install git+https://github.com/riscv/riscof

RISC-V GNU Compiler Toolchain should be prepared in advance. You can obtain prebuilt GNU toolchain for riscv32-elf from the Automated Nightly Release. If ENABLE_SYSTEM=1 was previously set, run make distclean before proceeding.

Run tests

Run all tests:

$ .ci/riscv-tests.sh

Or run it with the configuration you want:

$ make arch-test ENABLE_ARCH_TEST=1 <your-config>

For macOS users, installing sdiff might be required:

$ brew install diffutils

To run the tests for a specific set of extensions, set the environment variable RISCV_DEVICE to a concatenated ISA extension string. setup.py in tests/arch-test-target/ matches substrings against E, I, M, A, F, C, Zba, Zbb, Zbc, Zbs, Zicsr, Zifencei. The default is IMACFZicsrZifencei. Examples used by CI (.ci/riscv-tests.sh):

$ make ENABLE_ARCH_TEST=1 arch-test RISCV_DEVICE=IMAFCZicsrZifencei
$ make ENABLE_ARCH_TEST=1 arch-test RISCV_DEVICE=FCZicsr
$ make ENABLE_ARCH_TEST=1 arch-test RISCV_DEVICE=IMZbaZbbZbcZbs
$ make ENABLE_ARCH_TEST=1 arch-test RISCV_DEVICE=E
$ make ENABLE_ARCH_TEST=1 arch-test RISCV_DEVICE=IMC

Current progress

Passed Tests (RV32):

  • I: Base Integer Instruction Set
  • E: RV32E Base Integer Instruction Set
  • M: Standard Extension for Integer Multiplication and Division
  • A: Standard Extension for Atomic Instructions
  • F: Standard Extension for Single-Precision Floating-Point
  • C: Standard Extension for Compressed Instruction
  • Zba: Standard Extension for Address Generation Instructions
  • Zbb: Standard Extension for Basic Bit-Manipulation
  • Zbc: Standard Extension for Carry-Less Multiplication
  • Zbs: Standard Extension for Single-Bit Instructions
  • Zifencei: Instruction-Fetch Fence
  • privilege: RISCV Privileged Specification

References