SDRAM-Verification
February 25, 2017 ยท View on GitHub
This is a verification project. We are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed by "Dinesh in Opencores.org".
February 25, 2017 ยท View on GitHub
This is a verification project. We are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed by "Dinesh in Opencores.org".