README

Our paper is accepted by TACO'24 https://dl.acm.org/doi/abs/10.1145/3663479

This repo contains the codes simulating CXL 1.0 type-3 memory devices:

1. credit based flow control
2. flit packaging constrains
3. memory related commands, such as MemRd, MemWr, Cmp, and MemData
4. latency and bandwidth

You can check the codes src/mem/cxl_*, and an example config file config/example/CXLtest.py.

This is the gem5 simulator.

The main website can be found at http://www.gem5.org