Hardcaml Documentation

Welcome to Hardcaml!

I have written this by hand for sharing in the github repo, as our indexes are built automagically. There could be errors.

Each section explains different aspects of hardware design using Hardcaml, with sub-sections containing multiple examples written in Verilog, VHDL, and Hardcaml for comparison.

1. Introduction
   • 1.1 Why Hardcaml
   • 1.2 Installing the opensource release
   • 1.3 Quick overview
   • 1.4 FAQ
2. Designing Circuits
   • 2.1 Combinational Logic
     • 2.1.1 ROM
     • 2.1.2 Mux4
     • 2.1.3 Priority Encoder
     • 2.1.4 Parity
     • 2.1.5 ALU
   • 2.2 Sequential Logic
     • 2.2.1 JK Flip Flop
     • 2.2.2 T Flip Flop
     • 2.2.3 D Flip Flop
     • 2.2.4 Ring Counter
     • 2.2.5 Mobius Counter
     • 2.2.6 Modulo N Counter
     • 2.2.7 Gray Counter
     • 2.2.8 Bidirectional Shift Register
     • 2.2.9 Single Port RAM
     • 2.2.10 Synchronous FIFO
   • 2.3 Circuits
   • 2.4 RTL Generation
3. Simulating Circuits
   • 3.1 Simulating with Cyclesim
   • 3.2 Waveforms
   • 3.3 Interactive Viewer
4. More On Circuit Design
   • 4.1 Naming
   • 4.2 Always DSL
     • 4.2.1 BCD Conversion
     • 4.2.2 Cylon Eye
   • 4.3 Designing State Machines
     • 4.3.1 Sequence Detector
     • 4.3.1 Double Dabble
   • 4.4 Instantiation
   • 4.5 Working With Structural
5. Using Interfaces
   • 5.1 Hardcaml Interfaces
   • 5.2 Interfaces with ppx_hardcaml
   • 5.3 Module Interfaces
   • 5.4 Simulating with Interfaes
   • 5.5 Enums in Hardcaml
     • 5.5.1 Typed ALU
   • 5.6 Scopes
   • 5.7 Module Hierarchies
   • 5.8 Naming with ppx_hardcaml
6. Examples
   • 6.1 Counter
   • 6.2 Serial multiplier
   • 6.3 Fibonacci numbers
   • 6.4 FFT
   • 6.5 Binary Search
   • 6.6 Quicksort